Be an integral member of an experienced, international R&D team that is responsible for the architecture of new, differentiating, digital IP acceleration domains used in the design of advanced microcontrollers and microprocessors-based chips. The technology for which this team is responsible provides market differentiation of a product portfolio with over four billion USD in annual revenue. Chances are that the car you drive, the intelligent devices that pervade your living space, and the factories that produce the goods you use will contain one or more of the chips that you contribute to.

We are part of MCU/MPU Engineering, a central design organization within NXP, developing products for multiple business lines in Automotive, Internet of Things (IoT), Networking, and Radio Frequency products, with expertise in hardware engineering, including architecture, IP, and full SoC Design.

Job Summary:

• We are looking for a Senior Principal or Principal Processor Architect to research, develop, and advance the state-of-the-art in Artificial Intelligence (AI) accelerator IPs used in various products for different applications.

• Knowledge of the latest neural network architectures and methods of reduction to embedded implementations with real-world cost/power constraints is key to success in this role. 

• Responsibilities will include participation and tracking technical forums and literature. The role requires up-to-date knowledge of recent trends in industry and academia.

• Expertise in RTL design, C++/Python software design, and/or advanced Computer Architecture will be necessary to direct the activities of other members of the team doing this type of work.

• The candidate will be a senior member of a dynamic and innovative team, pushing the rapidly evolving AI/ML technology forward.

Key Challenges:

• You will leverage broad technical skills in software, firmware, hardware, and computer architecture to solve problems spanning all of these domains.

• Fast problem-solving will be a critical skill as the product life cycle matures and gets closer to chip tape-out.

Cross-functional aspects:

• You will be required to interact with many external teams including those leading the development of software tools and compilers, SOC performance models, and logic design and verification. Most of the external teams are located in other regions of the world such as North America or Asia. Thus, excellent communication skills are required to be successful in this role.

• The digital IP team is led by Directors and Fellows with many years of domain experience to leverage and further develop skills valuable as you advance your career.

Job Qualifications:

• Degree: Ph.D. preferred, minimum M.Sc. in Electrical Engineering, Computer Engineering, or a related subject

• 4+ (Ph.D.) or 7+ (M.Sc.) years of relevant work experience

• Experience with C/C++ for embedded and Python programming

• Knowledge of state-of-the-art neural network architectures such as CNNs, Transformers, or LSTMs

• Experience with ML frameworks for model construction and training (e.g. TensorFlow, PyTorch, TVM) and edge deployment (e.g. TensorFlow lite, MicroTVM)

• Knowledge of Networks-on-Chip architectures and tooling (e.g. mappers) is a plus

• Knowledge of RISC-V instruction set architecture is a plus

• Familiarity with the LLVM/MLIR compiler is a strong plus, but not required

• Good written and verbal English communication skills are required

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